// IF/ID pipeline reg 

module IF_ID(
    input clk,
    input rst_n,

    input [31:0] PC_in,
    input [31:0] PC4_in,
    input [31:0] Inst_in,
    input flush,
    input IF_stall_in,
    input IF_addr_fault_in,

    output [31:0] PC_out,
    output [31:0] PC4_out,
    output [31:0] Inst_out,
    output IF_stall_out,
    output IF_addr_fault_out

);
    reg [31:0] PC, PC4, Inst;
    reg IF_stall;
    reg IF_addr_fault;
    
    always @(posedge clk) begin
        if(rst_n == 1'b0)
        begin 
            PC <= 32'hbfc00000;
            PC4 <= 32'hbfc00000;
            Inst <= 0;
            IF_stall <= 0;
            IF_addr_fault <= 0;
        end
        else begin
            PC <= PC_in;
            PC4 <= PC4_in;
            Inst = flush ? 0 : Inst_in;
            IF_stall = IF_stall_in;
            IF_addr_fault <= IF_addr_fault_in;
        end
    end

    assign PC_out = PC;
    assign PC4_out = PC4;
    assign Inst_out = Inst ;
    assign IF_stall_out = IF_stall;
    assign IF_addr_fault_out = IF_addr_fault;
endmodule // IF_ID